TXUNFIS=Val_0x0, TXUIE=Val_0x0, RXOIE=Val_0x0, RXOVFIS=Val_0x0
Queue 0 Interrupt Enable and Status Register
| TXUNFIS | Transmit Queue Underflow Interrupt Status This bit indicates that the transmit queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0 (Val_0x0): Transmit queue underflow interrupt status not detected 1 (Val_0x1): Transmit queue underflow interrupt status detected |
| TXUIE | Transmit Queue Underflow Interrupt Enable When this bit is set, the transmit queue underflow interrupt is enabled. When this bit is reset, the Transmit Queue Underflow interrupt is disabled. 0 (Val_0x0): Transmit queue underflow interrupt status is disabled 1 (Val_0x1): Transmit queue underflow interrupt status is enabled |
| RXOVFIS | Receive Queue Overflow Interrupt Status This bit indicates that the receive queue had an overflow while receiving the packet. If a partial packet is transferred to the application, the overflow status is set in RDES3[21]. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0 (Val_0x0): Receive queue overflow interrupt status not detected 1 (Val_0x1): Receive queue overflow interrupt status detected |
| RXOIE | Receive Queue Overflow Interrupt Enable When this bit is set, the receive queue overflow interrupt is enabled. When this bit is reset, the Receive Queue Overflow interrupt is disabled. 0 (Val_0x0): Receive queue overflow interrupt is disabled 1 (Val_0x1): Receive queue overflow interrupt is enabled |